Nvidia is gonna Rock the industry

[rookal]

Nvidia Announces Maxwell-Powered Tegra X1 SoC At CES


Specs of this super-chip.

SoC system on a chip architecture.

TSMCs 20nm process
4 64bit ARM A53 cores ( ARMv8 processor capable of seamlessly supporting 32-bit and 64-bit code)
The A53 has a highly efficient 8-stage in-order pipeline balanced with advanced fetch and data access techniques for performance.
TrustZone® security technology
NEON™ Advanced SIMD (Can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. Also useful in accelerating floating point code with SIMD execution)

DSP & SIMD extensions
VFPv4 Floating point
Hardware virtualization support
1-4X SMP within a single processor cluster
ARM v8 architecture
Hardware-accelerated cryptography
Automatic event signalling
Load Acquire, Store Release instructions
Large Physical Address reach (beyond 4GB memory)
64-bit Virtual address reach
Double Precision Floating Point SIMD
64k pages
Large PC-relative addressing range



4 ARM Cortex A-57 processors
ARMv8-A 64-bit instruction set
L1 cache80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core
2 MiB shared L2 Cache (16-way set-associative, banked)
Pipelined processor with deeply out of order, speculative issue 3-way superscalar execution pipeline.
DSP and NEON SIMD extensions are mandatory per core
VFPv4 Floating Point Unit onboard (per core)
Hardware virtualization support
Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
TrustZone security extensions
Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
Hardware-accelerated cryptography
Wide multi-issue capability
1024 entry mail TLB
Large uTLBs
Advanced Branch Predictor
Optimized D-Size memory system (Sophisticated multi-stream L1 hardware prefetcher, exhaustive store/data-forwarding capabilities increase data throughput to the main datapath.
)

Extensive power-saving features

It uses two Image Signal Processors (ISP) to process a total of 1.3 Gpixels/s from up to six camera inputs. It also supports image sensors up to 100 MP
As for video, Tegra X1 encodes 4K video at 30 fps in either H.264, H.265, or VP8 formats in hardware, and can decode 4K H.265 (with 10-bit color depth) and VP9 video at 60 fps, also in hardware. It also supports the HDMI 2.0 interface for external displays.
ISP
AUDIO Engine
USB 3.0
LPDDR4 Meory controller
security offloads
e-MMC 5.x flash
MIPI DIS EDP
SPI SDIO

Now are you ready for its main party piece.

This one SoC chip aslo has 256 CUDA cores allowing full GPU computing capabilites.
Peak FP16 GFLOPS = 1024 (1 TFLOP)
Peak FP32 GFLOPS = 512
16 texture units
16 Gtexels/s

25.6 GB/s DDR4 memory bandwidth
16 ROPs
256k L2 Cache
Draws 44% lower power than the Apple A8x


Tegra X1 is the first mobile SoC to exceed one TeraFLOPS of peak FP16 operations and over 500 GFLOPS at FP32. Compared to ASCI Red, the first supercomputer to break one TeraFLOP on the LINPACK benchmark and the world's fastest supercomputer until the year 2000, this is quite an accomplishment, especially considering it used almost 1600 square feet of space, 9,298 Intel Pentium Pro processors running at 200 MHz, and required 850 kW of power

[cookiedough]

Nothing new here from NVIDIA. Mediatek announced the same setup eleven months ago. 4 Cortex A57 in big.LITTLE with 4 Cortex A53 (A53 for low intensity tasks).

Source: MT6732 & MT6752

[WuddaWaste]

I like the fact that it has a "main party piece". I like to party.